The Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU.
A Simplified VHDL UART A Simplified VHDL UART Introduction In embedded systems, the processor that we choose for our design may not come with built-in peripherals. Therefore, designers will have to implement these devices in hardware keeping in mind that they will need to interface to the processor. In this lab we will design a simplified UART (Universal Asynchronous Reciever Transmitter) in VHDL and download it to the FPGA on the XS40 baord. Serial communication is often used either to control or to receive data from an embedded microprocessor. Serial communication is a form of I/O in which the bits of a byte begin transferred appear one after the other in a timed sequence on a single wire. Serial communication has become the standard for intercomputer communication.
In this lab, we'll try to build a serial link between 8051 and PC using RS232. RS232C: The example serial waveforms in Fig 1 show the waveform on a single conductor to transmit a byte (0x41) serially. The upper waveform is the TTL-level waveform seen at the transmit pin of 8051. The lower waveform shows the same waveform converted to RS232C levels. The voltage level of the RS232C are used to assure error-free transmission over greater distances than would be possible with TTL levels. As shown in Fig 1, each byte is preceded by a start bit and followed by one stop bit.
The start and stop bits are used to synchronize the serial recievers. The data byte is always transmitted least-significant-bit first. For error checking it is possible to include a parity bit as well, just prior to the stop bit. The bits are transmitted at specific time intervals determined by the baud rate of the serial signal.
The baud rate is the reciprocal of the time to send 1 bit. Error-free serial communication requires that the baud rate, number of data bits, number of stop bits, and presence or absence of a parity bit be the same at the transmitter and at the receiver.
Serial Waveforms RS232 connector: PCs have 9pin/25pin male SUB-D connectors. The pin layout is as follows (seen from outside your PC): 1 13 1 5.
![Rf data transmitter circuit Rf data transmitter circuit](/uploads/1/2/5/3/125385204/359107681.png)
/ - - 14 25 6 9 Name (V24) 25pin 9pin Dir Full name Remarks - TxD 2 3 o Transmit Data RxD 3 2 i Receive Data RTS 4 7 o Request To Send CTS 5 8 i Clear To Send DTR 20 4 o Data Terminal Ready DSR 6 6 i Data Set Ready RI 22 9 i Ring Indicator DCD 8 1 i Data Carrier Detect GND 7 5 - Signal ground - 1 -Protective ground Don't use this one for signal ground! The most important lines are RxD, TxD, and GND. Others are used with modems, printers and plotters to indicate internal states.
In this lab, we are going to use, to communicate between the PC and the 8051. UART Clock Divider: The UART that we are designing will be transmitting data at a rate of 1200 baud, or 1200 bps. However, since the FPGA and 8051 on the XS40 board operates at 12 MHz, simply transmitting one bit every clock cycles will be too fast. Therefore, we will need to create a clock divider that will be used by the UART to transmit one bit per cycle. The input to the clock divider will be a 12 MHz clock and the output should be a 1200 Hz clock.
Apparatus Required:. 0.1 mF capacitors(6). Serial Connector. Serial Cable. XS40 Board Schematic: Procedure:.
Download the following files:. Modify main.c to send each character and wait for the acknowledge signal from the UART. Modify uartclkdiv.vhd to complete the functionality of the clock divder to create a clock for 1200 bps (1200 Hz). Modify uart.vhd to complete the UART. NOTE: Becuase the CPU read/write process and UART transmit process have different clock signals as input, it will be neccessary to use handshaking signals between the two. Compile, synthesisze, and download the 8051 program and UART to the FPGA. NOTE:If you are unsure of how to compile and download, refer to the.
There are some basic principles. First thing you can do is study the operation of a UART of any 8 bit microcontroller, and you will know the registers, signals, control involved. In that kind of receiver-transmitter, the receiver is more complex than the transmitter. The transmitter consists only of a state machine of N states depending on the number of bits of the serial transmission. The bit generated on each state depends on the bits stored in the TX register. In the receiver side it has to detect the start bit, and then pick up the transmited data bits, usually they do this by sampling data at a frequency higher than the UART transmission rate, once it detecs the start bit you synchronize the state machine with UART clock and pick up the data bits, then store them in the RX register.
Basically that´s what you have to do. Quote:' Another, more basic UART project from Quote: but i didnt find anything matches my likings You may rather like to design your own UART, it isn't that difficult and instructive anyway.' Hello all, I just surfed in looking for a VHDL tutuorial demonstrating RS232 communications. I'm just starting with VHDL and have the Digilent Virtex-II development system with the ISE 10.1 and Impact 10.1 software packages: To date, with help I've only managed to write a simple program to respond to some of the switches and digital inputs to control the on-board digital led's.
I'm an experienced C programmer, and have even done some PLC programming, but this environment is very foreign to me. I would love to reverse engineer the example from above, but I'm too green to know how to hook up all those vhd files with my ucf files, and fire this thing up. Does anybody have a walk-through of this example loaded up, locked and loaded that I can follow? And since I want the world, I'm going to have to expand this example to some data processing. Now in C I'd throw all the ascii characters in a nice string array, and then do some strstr functions looking for my command strings, and then send some nice ascii strings out another UART and an ACK back to the source UART, but I'm not even sure how the idea of strstr and character buffers works in this VHDL world. Ok, santa that's about it, any help out there? TIA, Jonathan.
Ok, I'm going through this chapter. Its very well written, and I've even gone ahead and ordered the book its from.
Quick question. The article introduces on book in section 7.2.4 A flag FF. What is a Flag FF?
Does the FF stand for flip flop? I can't find a definition. Sincerely, Jon Oh Sorry! Some files are missing in that file. It refers to the previous chapters. Download all chapters here.!!! In this chapter FF means Flag pointer for First in Fast Out Buffer.
Okie enjoy it. I just picked up a copy of the whole book, hard copy and even the pdf for searching. It's a great book. I'm going through it now (I'm scared to lock and load, and just run the RS232 example.) This is great stuff. Its all clicking now, this is exactly what I wanted, I just read up on the circular FIFO buffer, love it. In the example they haven't mentioned the.UCF file, I just started with chapter 1, but I imagine that I have to resolve RX and TX to the pinouts of my evaluation board. I'll be posting my progress (more likely questions) as I go.
Here's my version of a blog on how to get this UART working. Its a complete backup of my workspace on the project in its natural tree form, and there is also a zip file of the project if you want to download it in one fail swoop (3mb) the backup is here: and the zip file of that is here: You will also notice a notes sub-directory where these notes and discoveries are being documented here: I even used microsoft word to try and clean up the notes.txt file a bit.
Anyway, here is the project so far, and I'd appreciate some insight as detailed in step 6) below. Jon Notes.txt: 090120 - ok so I started this project and I admit it, I'm scared and I don't really know what I'm doing. I have the Digilent Virtex-II development system with the ISE 10.1 and Impact 10.1 software packages: This project started with the sources and chapter 7 of: FPGA PROTOTYPING BY VHDL EXAMPLES Xilinx SpartanTM-3V ersion Pong P. Chu Cleveland State University the authors website has even a download of the examples: and even chapter 7 as a pdf file: In this backup of my project, all the examples from the book are stored in this tree as vhdlexamples and all the sources I think I need are stored in orig because I'm sure I'll be modifying them and so I wanted to store off my originals. As I make milestones, I imagine new directories of backups will emerge, named buxxsomethingdescriptive as this forray will also be kept online, I will zip it up and store it in the root directory under zipYYMMDDxsomethingdescriptive.zip so anyone wishing to follow in my footsteps or play along can do so. With that said lets begin. 1) I started a new project with ISE 10.1 Project Navigator.
2) after that huba-balloo, I clicked 'add existing source' and added all the source I thought I needed from the examples. I had previously put copies of those sources in the root of the project. I even took a screencap: notes screencap01firstsource.png so far so good. 3) I then clicked 'synthesize -XST'.
The arrows chasing each other thingy changed after a few seconds to a spinny type thingy and the bottom view section started spewing all kinds of report stuff. All well and good and I ended up with some warnings, which I'd like to discuss a little later. Here's the screen cap: notes screencap02firstsynth.png the error messages are: Analyzing Entity in library (Architecture ). WARNING:Xst:753 - 'C:/jon/fpgauartjl01/uarttest.vhd' line 29: Unconnected output port 'dblevel' of component 'debounce'.
Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ).
DBIT = 8 DVSR = 163 DVSRBIT = 8 FIFOW = 2 SBTICK = 16 WARNING:Xst:753 - 'C:/jon/fpgauartjl01/uartcore.vhd' line 37: Unconnected output port 'q' of component 'modmcounter'. WARNING:Xst:753 - 'C:/jon/fpgauartjl01/uartcore.vhd' line 46: Unconnected output port 'full' of component 'fifo'. Entity analyzed. Unit generated. Now I haven't used a UCF file yet, and I believe that I must, so I'd like to discuss that in a very short time period, but let's continue with what I have done so far. 4) I then hit the 'implement design' arrow thingy. It was very obedient and started spinning as well.
Whe it was all done it was very happy. No errors or warnings. Here's the screen cap of that result: notes screencap03firstimplement.png 5) checking the pinouts. Well somewhere in my travels, someone mentioned looking at the pinout report for useful stuff.
So here it is: notes screencap04firstpinoutrpt.png 6) well now I want to take a break and review a few things, I can see that my pinout report has some useful stuff and some not-so useful stuff. For instance, RX and TX I think have to somehow be associated to the DB9 that is on my board (the root directory has a UCF file RS232.UCF in it, that I believe I should use, and the pinouts of this 'hard' uart should be properly level shifted yes?) This example also assumed a spartan 3 evaluation kit which I guess has a digital readout and I think that is what those led things are, so I want to get rid of those. I also have a question about the clock situation. The chapter describes that all the communication is to be synched up with a clock pulse divided by 16. something or other (see 7.2.2) now this is all well and good, but I imagine my system clock is different (ok, I admit it, I don't even know where it is.) and so those calculations need to be adjusted. So at this point I'm looking for advice and review of my work so far.
Can anybody give some insight into the issues I've raised in 6) above? Here is the latest of my build: ERROR:ConstraintSystem:59 - Constraint ERROR:ConstraintSystem:59 - Constraint ERROR:ConstraintSystem:59 - Constraint ERROR:ConstraintSystem:59 - Constraint ERROR:ConstraintSystem:59 - Constraint ERROR:ConstraintSystem:59 - Constraint ERROR:ConstraintSystem:59 - Constraint notes screen05firstucferrors.png I don't know why it's just not ignoring the unused signals and now I realized that the UCF file uses the # as a comment out character instead of the the '-' grrrrrrr. Yup that's it. Notes screen06ucffixed.png notes screen07pinoutrpt.png Ok, this looks like a I successfully completed 'implement design' added clocks.ucf to move clock to AJ15.
All implimented still here's clocks.ucf: NET 'clk' LOC = 'AJ15'; NET 'clk' IOSTANDARD = LVCMOS25; NET 'clk' TNMNET = 'clk'; TIMESPEC 'TSclk' = PERIOD 'clk' 10.00 ns HIGH 50%; whatever this means. Now for the button,reset, and leds: btndbunit: entity work.debounce(fsmdarch) port map(clk=clk, reset=reset, sw=btn(0), dblevel=open, dbtick=btntick); - incremented data loop back recdata1.